CHENNAI : Indian Institute of Technology Madras (IIT Madras) is bringing together on one platform various stakeholders from the Government to academic to strengthen India’s journey towards becoming a global leader in semiconductor innovation.
IIT Madras is partnering with the Ministry of Electronics and Information Technology (MeitY), Government of India, and RISC-V International, the non-profit home of the open standard RISC-V Instruction Set Architecture (ISA), to host the 3rd Digital India RISC-V (DIR-V) Symposium 2026. It will be held 1st – 2nd August 2026 at IIT Madras Research Park in Chennai, Tamil Nadu.
The last Date to register for this event through the following link is 28th July 2026 – https://dirv.iitm.ac.in
The symposium aligns with the Government of India’s vision to establish India as a trusted global hub for semiconductor design, electronics manufacturing, and secure digital infrastructure.
The symposium will bring together leading policymakers, global technology experts, researchers, startups, industry leaders, investors, faculty members, and students to work on this year’s theme of ‘Empowering Bharat’s Semiconductor Future’.
This year’s symposium focuses on advancing indigenous processor technologies, secure computing systems, hardware innovation, AI and the rapidly expanding RISC-V ecosystem. The event aims to promote collaboration between government, academia, research institutions, startups, and industry to build trusted semiconductor technologies designed and developed in India.
Highlighting the need for such symposiums, Prof. V. Kamakoti, Director, IIT Madras, said, “The Digital India RISC-V Symposium was created to bring together the entire semiconductor ecosystem – government, industry, academia, startups, and researchers to collectively build India’s indigenous computing capabilities. The overwhelming response to the first two editions reaffirmed our confidence that India possesses both the intellectual capital and the innovation ecosystem to become a global leader in semiconductor technologies.”
Prof. V. Kamakoti added, “As India’s digital economy expands, secure and trusted semiconductor technologies have become a strategic national priority. The third edition of the symposium reflects this vision by creating a platform where researchers, innovators, startups, industry leaders, and policymakers can collaborate to build secure, intelligent, and globally competitive silicon designed in India for the world.”
Building on the success of its first two editions, the Digital India RISC-V Symposium has emerged as one of India’s premier platforms for discussing the future of open processor architectures and indigenous semiconductor development. The symposium continues to support the national vision of Atmanirbhar Bharat.
Over two days, participants will have the opportunity to engage with leading experts through keynote addresses, technical sessions, panel discussions, hands-on workshops, technology demonstrations, exhibitions, startup showcases, and networking sessions. The programme will also feature the DIR-V Grand Challenge Hackathon, highlighting innovative solutions developed by students and startups using RISC-V technologies. retain these lines
It will provide participants with opportunities to interact directly with experts from academia, government, industry, RISC-V International, and India’s growing semiconductor ecosystem.
Participants can also explore live technology demonstrations, startup exhibits, and networking opportunities with leading organizations working in processor design, semiconductor technologies, embedded systems, AI hardware, and cybersecurity.
By encouraging open collaboration around the RISC-V architecture, IIT Madras continues to play a pioneering role in developing indigenous processor technologies, nurturing deep-tech startups, and building a skilled semiconductor workforce for the future.
